The present invention relates to a method for designing a semiconductor device provided with decoupling capacitors, and more particularly, to a layout method of decoupling capacitors.
In recent years, semiconductor devices have become faster and larger thereby increasing power consumption. The increase in power consumption may cause power supply noise that would interfere with stable operation of the semiconductor device. Therefore, decoupling capacitors are provided between a high voltage power supply line and a low voltage power supply line in the semiconductor device. For a semiconductor device including such decoupling capacitors, it is required that the decoupling capacitors be efficiently laid out to reduce the number of design processes.
In a process for designing a semiconductor device in the prior art, FIG. 1 shows the procedure for determining the layout of logic cells. Each logic cell is a cell unit including a plurality of logic circuits. The decoupling capacitor suppresses power supply noise that is generated when the logic cells are activated.
First, in step S1, the logic cells are laid out. In step S2, wires are routed to connect the logic cells to one another. Before the layout of the logic cells, wires connecting functional blocks, such as an analog signal circuit block or a CPU core, are laid out. In each functional block, the decupling capacitor is laid out beforehand.
After locating the logic cells, in step S3, the decoupling capacitors are laid out in the areas that are unoccupied. In step S4, the areas in which the logical cells are laid out are equally divided to define grid areas. Then, the power consumption of the logic cell in each grid area is calculated.
In step S5, the decoupling capacitance that is necessary for each grid area is calculated. Then, in step S6, the decoupling capacitance of the decoupling capacitors laid out in step S3 is compared with the capacitance calculated in step S5 for each grid area to determine whether the decoupling capacitance necessary for the power consumption is allocated to each grid area.
When the necessary decoupling capacitance is allocated in every one of the grid areas, the layout of the logic cells and the decoupling capacitors is completed. If there is a grid area to which the necessary decoupling capacitance is not allocated, the logic cells are re-laid out (step S7). Then, steps S2 to S6 are repeated.
Japanese Laid-Out Patent Publication No. 2003-256489 describes a first prior art method including a step for laying out functional blocks and input/output blocks and a subsequent step for laying out unit cell capacitor blocks that serve as decoupling capacitors in unoccupied areas.
Japanese Laid-Out Patent Publication No. 2002-288253 describes a second prior art method including a step for dividing a chip into a plurality of grids, a step for determining whether the decoupling capacitance necessary for the power consumption is allocated in each grid, and a step for increasing a macro-area when the decoupling capacitance is insufficient.